This invention relates to reference clock receivers for use with Programmable Logic Devices (PCDs) or any other suitable electronic device.
Clock multiplier phase-lock loops (PLL) in transceivers usually require a “clean” reference clock that is generated from an external crystal clock source. The output voltages of the crystal are typically differential voltages. These voltages may be compliant with different standards such as LVPECL (Vcm=1.8825 volts˜2.05 volts), LVDS (Vcm=˜1.25v volts), and PCI-Express (Vcm=0.25 volts˜0.55 volts). Then a reference clock receiver is needed to take the differential signals with differential voltage levels and convert them to a signal level that is compatible with the core supply voltage in the high-speed serial interface portion of the PLD.
FIG. 1 shows a circuit that shows a conventional reference clock receiver structure 100. Reference clock receiver structure 100 includes input buffer 102, level shift 104, and CMOS buffer 106. The first stage input buffer 102, is a differential pair of transistors to receive differential inputs (IP and IN). The differential pair consists of thick oxide 3.3 volts devices to withstand higher voltage levels seen at the input of the structure.
The second stage is basically a level shift stage 104 and provides sufficient gain to increase signal swing.
The third stage 106 further boosts the input signal to provide CMOS level outputs. Duty-cycle connection of the signal is performed in this stage to reduce jitters.
For an input buffer with NMOS differential pair of transistors 202 and 204, as shown in FIG. 2, the lower end of input common mode range is limited to Vgstransistor 202/transistor 204+VdSATtransistor 212. Resistors 206 and 208 also are used with the differential pair and transistor 210 forms a current mirror together with transistor 212.
As stated above, in order to be tolerant of high voltage input signals, NMOS differential pair 202 and 204 should be formed from thick oxide. As such, this NMOS-based differential pair's lowest common-mode voltage is sub-optimal because thick oxide devices have larger threshold voltages. In such circumstances, input common-mode voltage could be relatively very high (e.g., above 1 volt). This conventional structure may not be able to meet specifications of certain new industry standards such as PCI-Express, whose reference clocks have a common-mode range from 0.25 volts to 0.55 volts.
It would be desirable to provide a receiver clock structure that is able to accommodate a relatively wide input common-mode range.
It would also be desirable to provide a receiver clock structure that includes a differential pair formed from relatively thick oxide structures while still being able to accommodate a relatively wide input common-mode range.